十进制计数器 vhdl
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共2个回答
热心网友
LIBRARY
IEEE;TY
CNT10
IS
&n
USE
IEEE.STD_LOGIC_11.ALL;
USE
IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY
CNT10
ISEE.STD_LOGIC_11.AL
PORT
(CLK,RST,EN
:
IN
STD_LOGIC;
CQ
:
OUT
STD_LOGIC_VECTOR(3
DOWNTO
0);
COUT
:
OUT
STD_LOGIC
);
L;
USE
IEEE.STD_LOGI
END
CNT10;
ARCHITECTURE
behav
OF
CNT10
IS
BEGINC_UNSIGNED.ALL;
ENTI
PROCESS(CLK,
RST,
EN)
VARIABLE
CQI
:
STD_LOGIC_VECTOR(3
DOWNTO
0);
BEGINLIBRARY
IEEE;
USE
IE
IF
RST
=
'1'
THEN
CQI
:=
(OTHERS
=>'0')
;
--计数
ELSIF
CLK'EVENT
AND
CLK='1'
THEN
L;
USE
IEEE.STD_LOGI
IF
EN
=
'1'
THEN
IF
CQI
<
9
THEN
CQI
:=
CQI
+
1;
--允许计数,
TY
CNT10
IS
&n
ELSE
CQI
:=
(OTHERS
=>'0');
--大于9，
END
IF;C_UNSIGNED.ALL;
ENTI
END
IF;
END
IF;
IF
CQI
=
9
THEN
COUT
<=
'1';
--计数大于9，输出进位信号LIBRARY
IEEE;
USE
IE
ELSE
COUT
<=
'0';
END
IF;
CQ
<=
CQI;
--将计数值向端口输出L;
USE
IEEE.STD_LOGI
END
PROCESS;
END
behav;
热心网友
LIBRARY IEEE;TY CNT10 IS &n
USE IEEE.STD_LOGIC_11.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 ISEE.STD_LOGIC_11.AL
PORT (CLK,RST,EN : IN STD_LOGIC;
CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT : OUT STD_LOGIC ); L; USE IEEE.STD_LOGI
END CNT10;
ARCHITECTURE behav OF CNT10 IS
BEGINC_UNSIGNED.ALL; ENTI
PROCESS(CLK, RST, EN)
VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGINLIBRARY IEEE; USE IE
IF RST = '1' THEN CQI := (OTHERS =>'0') ; --计数
ELSIF CLK'EVENT AND CLK='1' THEN L; USE IEEE.STD_LOGI
IF EN = '1' THEN
IF CQI < 9 THEN CQI := CQI + 1; --允许计数,
TY CNT10 IS &n
ELSE CQI := (OTHERS =>'0'); --大于9，
END IF;C_UNSIGNED.ALL; ENTI
END IF;
END IF;
IF CQI = 9 THEN COUT <= '1'; --计数大于9，输出进位信号LIBRARY IEEE; USE IE
ELSE COUT <= '0';
END IF;
CQ <= CQI; --将计数值向端口输出L; USE IEEE.STD_LOGI
END PROCESS;
END behav;
